Recently, there is an increasing demand for display devices of lighter weight, higher-definition, thinner, lower power consumption and larger display area for AV equipments such as home-use TVs, OA equipments, etc. Examples of such display devices include CRT (Cathode-Ray Tube) displays, LCDs (Liquid Crystal Display), plasma displays, EL (Electroluminescent) displays, LED (Light Emitting Diode) displays, etc.
Among the described display devices, the use of the liquid crystal displays has achieved wide-spread acceptance in a variety of fields recently. The LCDs have an advantage over other display devices in that they can be installed even in a small space with ease and requires small power consumption because of its beneficial characteristics of thinner structure compared with other display devices. Moreover, as the LCDs are evolvable into full-color display with ease, they can be suitably applied to display devices of a large-sized display area. Thus, the LCDs are the best candidate for large-sized display area.
On the contrary, when upsizing the active matrix liquid crystal display device, an occurrence of a defect such as a disconnection of a line such as a signal line, a scanning line or a pixel defect, etc., significantly increases in the manufacturing process which raises the problem of an increase in a manufacturing cost. A solution to the described manufacturing method is disclosed, for example, by Japanese Unexamined Utility Model Publication No. 191029/1985 (Jitsukaisho 60-191029). This publication discloses a liquid crystal display device adopting a large substrate by connecting small substrates for at least one of the pair of substrates with electrodes.
FIG. 11(a) is a plan view of the above liquid crystal display device, and FIG. 11(b) is a cross-sectional view of the same taken along a line B-B' Specifically, a large substrate is prepared by connecting four active matrix substrates (hereinafter referred to as TFT substrates) 52 through 55 side to side to be positioned adjacently in a longitudinal direction and a lateral direction. Further, the resulting large substrate and a counter substrate (CF substrate) 51 with an electrode whereon color filters are formed are connected together via a spacer 57 so as to sandwich a liquid crystal layer 50.
Generally, when adopting the active matrix liquid crystal display device, it is difficult to manufacture at high yield the TFT substrate whereon fine active elements and pixel electrodes 71 which are provided for respective pixels are formed in a matrix in a large area. In order to counteract the described problem, a TFT substrate as one of the pair of substrates which constitute the liquid crystal display device is prepared using a plurality of small substrates, and a large TFT substrate is realized by connecting the small substrates side to side, and further by connecting the resulting large TFT substrate to the counter substrate which is the other large substrate having color filters to realize a large screen panel. As a result, an improved yield of the manufacturing process can be achieved.
In order to achieve an improved productivity, another large screen liquid crystal display device which is realized by connecting a plurality of liquid crystal panels side to side on a plane is disclosed by Japanese Unexamined Patent Publication No. 122769/1996 (Tokukaihei 8-122769).
FIG. 15(a) and FIG. 15(b) respectively show a plan view and a cross-sectional view of the liquid crystal display device. The left and right active matrix liquid crystal display panels 81 and 82 are connected side to side on the reinforcing substrate 83 by a bonding agent 84 to realize a large screen liquid crystal display device. The panels 81 and 82 respectively include TFT substrates 85 and 86, and counter substrates (CF substrates) 87 and 88 having electrodes and color filters formed thereon are connected together so as to sandwich a liquid crystal layer 89 using a seal 90. The seal 90 is formed at peripheral portion of each liquid crystal display panel, and the liquid crystal layer 89 is sealed within the seal 90. According to the liquid crystal display device of the described arrangement, by connecting the maximum size of the liquid crystal display panels that can be manufactured using the existing facilities, a large screen liquid crystal display device can be manufactured without requiring an installation of additional facilities for large size liquid crystal display device.
However, the described liquid crystal display device has the following drawbacks.
Japanese Unexamined Utility Model Application No. 191029/1985 (Jitsukaisho 60-191029) adopts a large size TFT substrate prepared in such a manner that a plurality of TFT substrates 52 through 55 are prepared beforehand, and the resulting TFT substrates 52 through 55 are connected side to side. As been well known, on the TFT substrate, formed are scanning lines (gate bus line) 72 and signal lines (source bus line) 73 in a matrix, and active elements 79 adopting thin film transistors (TFT elements) as switching elements and pixel electrodes 71.
As is clear from FIG. 11(a), for all the small TFT substrates 52 through 55 which constitute the large TFT substrate, the arrangement with regard to the relative position between (a) the signal lines 73 and the scanning lines 72 which are formed in a matrix and (b) the active elements 70 and the pixel electrodes 71 is the same. Specifically, for all the TFT substrates 52 through 55, (i) the active elements 79 composed of TFTs having gate electrodes connected to the signal lines 72 and (ii) the pixel electrodes 71 to be connected to the drains of the TFTS (ii) are formed on the right side of the signal lines 73 extending substantially parallel to a connecting side (Y-direction in the figure) between the TFT substrates 52 and 53 and below the signal line 72 extending in a line substantially orthogonal to the connecting side (X-direction in the figure).
FIG. 12 is an enlarged plan view showing a portion in a vicinity of the connecting area between the upper left TFT substrate 52 and the upper right TFT substrate 53. These upper left and right substrates 52 and 53 are connected via a connecting area using a bonding agent 56. It is preferable to arrange such that a pixel pitch in a region including the connecting area 60 is equal to a pixel pitch of a pixel region of the TFT substrates 52 and 53 to connect these substrates 52 and 53 smoothly. Therefore, the connecting face of each TFT substrate is required to be processed very smoothly with high precision and to make the connecting area 60 narrow.
However, when adopting a scribe cut method when cutting the TFT substrate from a mother glass into a predetermined size, as protrusions and recessions of around 0.5 mm are formed on the cut surface, it is impossible to obtain a smooth cut surface. Therefore, it is required to use a dicing device adopting the diamond blade in order to obtain a desirable smoothness of the cut surface. By adopting the dicing device, protrusions and recessions formed on the cut surface can be reduced to be not more than 0.05 mm.
Even in the case of adopting the dicing device, as shown in FIG. 13, fine defects (chipping) 63 may be formed along the edge of the cut surface of the TFT substrate 53. For example, by experience, when cutting the substrate by dicing under the conditions shown in Table 1, in the case of cutting the mother glass having a length of 550 mm, a width of 650 mm, and a thickness of 1.1 mm in a lateral direction, many small chippings (chipping width W of not more than 0.01 mm) and a few large chippings (chipping width W in a range of from 0.03 to 0.05 mm) are formed in a cut length of 650 mm.
TABLE 1 ______________________________________ Dicing Conditions ______________________________________ WORK TYPE GLASS SUBSTRATE FOR LIQUID CRYSTAL PANEL WORK SIZE 550 mm * 650 mm *1.1mmt (MOTHER GLASS SIZE) 420 mm * 620 mm *1.1 mmt (CUT SIZE) BLADE TYPE DIAMOND BLADE #400 BLADE SIZE DIAMETER 127 mm THICKNESS 0.3 .mu.m NUMBER OF ROTATION 12000 rpm OF SPINDLE CUT SPEED 2 to 3 mm/s ______________________________________
By optimizing the dicing conditions, an occurrence of large chippings having a chipping width W of from 0.03 to 0.05 mm may be reduced; however, it is not possible to eliminate an occurrence of large chippings under manufacturing conditions which meet a demand for an improved productivity.
When large chippings (chipping width W in a range of from 0.03 to 0.05 mm) are formed in a connecting area of the TFT substrates, the following problems arise.
FIG. 14 is an enlarged plan view showing a vicinity of the connecting area when connecting the left and right TFT substrates 52 and 53 having chippings 63 in the connecting area. As shown in the figure, the chippings 63 formed when cutting by dicing may cause a disconnection of the signal line 73 adjacent to the connecting side of the right TFT substrate 53. Such chippings 63 may even cause a damage on the active element 70. As described, a large chipping 63 may significantly lower the productivity of the liquid crystal panel, but small chippings do not seriously affect the productivity by causing, for example, signal line disconnection.
Therefore, the structure which can eliminate a damage on a signal line or an active element even if large chippings (chipping width W of from 0.03 to 0.05 mm) occur along the edge of the TFT substrate 53 is desired.
As shown in the plan view of FIG. 15(a) and the cross sectional view of FIG. 15(b), the arrangement wherein the liquid crystal display panels 81 and 82 are connected has been proposed. As shown in FIG. 16, on the TFT substrates 85 and 86 for the liquid crystal display panel, formed are scanning lines (gate bus line) 91 and signal lines (source bus line) 92 in a matrix, and active elements (TFT elements) 93 and pixel electrodes 94 provided at respective junctions of the matrix. As described earlier, the seal 90 is formed in a flame along the circumference of each of liquid crystal display panels 81 and 82, and a liquid crystal layer 89 is enclosed inside the seal 90 formed in a flame. FIG. 16 is an enlarged plan view of the TFT substrates 85 and 86 in a vicinity of a connecting area of the left and right liquid crystal display panels 81 and 82 of the liquid crystal display device shown in FIG. 15(a) and FIG. 15(b).
The left and right TFT substrates 85 and 86 are connected via the connecting area 80 using the bonding agent 84, and the seal 90 for connecting the CF substrates 87 and 88 is formed along the connecting side of the TFT substrates 85 and 86. This seal 90 shows a seal pattern in a flame along the circumference of each of the liquid crystal display panels 81 and 82.
Here, by making the pixel pitch in the connecting area equal to the pixel pitch of other areas, a uniformity of the display can be achieved, and the connecting part becomes less outstanding. Thus, the seal 90 is required to be formed as narrow as possible, and to be formed adjacent to the pixel electrode 94 formed along the connecting side. Therefore, for the material of the seal 90, in order to avoid adverse effects on display pixel adjacent to the seal 90, such as display inferior, a photo-setting seal material whose shape is hardly affected when hardening is adopted.
However, in the case where the relative position of (i) the scanning lines 91 and the signal lines 92 formed in a matrix and (ii) the TFT substrate 93 and the pixel electrode 94 is the same between the left and right liquid crystal display panels 81 and 82, the following problems would arise in the arrangement shown in FIG. 16 where the scanning line 91, the TFT element 93 connected to the signal line 92 and the pixel electrode 94 are formed below the scanning line 91 extending in the X-direction and to the right of the signal line 92 extending in the Y-direction in the left and right TFT substrates 85 and 86.
Namely, in the case of connecting the TFT substrates 85 and 86 and the CF substrates 87 and 88 in a flame along the peripheral portion of the CF substrates 87 and 88, when hardening the seal resin by a projection of light by projecting light from the side of the CF substrates 87 and 88, light is blocked by the black matrix (BM) formed in a region facing the pixel electrode 94. Therefore, it is required to project light from the side of the TFT substrates 85 and 86. However, in the right TFT substrate 86, as shown in FIG. 16, as the seal 90 overlaps the signal line 92 formed along the connecting side, light may be blocked by the signal line 92, which causes a hardening inferior of the seal 90. This hardening inferior of the seal 90 adversely affects the display pixel adjacent to the seal 90 and causes, for example, a display inferior, etc.
In view of the above conventional problems, a development of an arrangement which prevents a hardening inferior of the seal 90 even when placing the display pixel adjacent to the seal 90 is desired.